Digital signal processors are well known devices for performing high-speed data manipulations. Digital signal processors often include circuitry directed to handling interrupts. Interrupts request attention from the digital signal processor and can be passed to the processor by either hardware or software. An interrupt conventionally causes the processor to suspend its current operations, save the status of its work, and transfer control to a special routine called an interrupt handler that causes a particular set of instructions to be carried out. A table stored in the processor's memory contains the address of a corresponding routine for each interrupt. The addresses are called pointers because they point to the beginning of the interrupt handlers.
Interrupts conventionally occur for a variety of reasons such as service requests from hardware devices and errors in processing. When a processor receives interrupt requests from more than one source, a hierarchy of interrupt priorities determines which of the interrupts is handled first. The hierarchy is conventionally designated by the design of the processor. If a constant stream of interrupt requests would disrupt or complicate processing at a critical point, the interrupts often may be temporarily disabled.
One type of interrupt is an analysis interrupt. An analysis interrupt is used to analyze the processor state while it is performing its functions, thus providing debugging capability. Thus, an analysis interrupt provides a mechanism for providing real time statistics concerning a processor's performance. An analysis interrupt may be originated by a host processor or may be generated internally. In either case, the analysis interrupt requires some of the processor's processing capabilities. Examples of information that may be obtained through an analysis interrupt include the contents of a portion of the processor's memory, the contents of one of its registers, or the location of the processor in executing a piece of software.
Because digital signal processors often operate in real time environments, it is important for the processor to accomplish its tasks in a timely fashion. Therefore, analysis interrupts, which require some of the processor's processing capabilities, are conventionally secondary to the functional tasks of the processor and are designated to have a low priority. The low priority status of analysis interrupts may preclude the rapid acquisition of analysis data. This can cause problems because analysis data may be required in a more timely fashion than is available through conventional low priority interrupts. However, designating analysis interrupts as high priority may result in poor performance by the processor if the processor requires the majority of its resources for other tasks.
Prior processors have therefore incorporated analysis interrupts having a configurable priority. One prior processor includes a priority bit stored in a register that is indicative of the priority assigned to an analysis interrupt. In that processor, if the priority bit has a first value, an analysis interrupt is assigned the lowest priority and is maskable. If the priority bit has a second value, an analysis interrupt is assigned the highest priority and is non-maskable. That prior processor also includes a stack for storing addresses of the next execute packets that were not executed due to interruption by an interrupt, such as an analysis interrupt or a standard interrupt. A stack is used because, since an interrupt may interrupt processing of a lower priority interrupt, multiple addresses of program locations may have to be stored.
The use of a stack to store memory locations of programs that were not executed due to an interrupt has been found, however, to be detrimental to the performance of a processor. The use of a stack requires a significant number of memory accesses over a large number of clock cycles and therefore can slow processing by the processor. In the same prior processor incorporating a configurable priority analysis interrupt, in order to generate an analysis interrupt, a user conventionally modifies the software operation code in memory to include a software trap instruction. The software trap instruction initiates the analysis interrupt. Such a procedure of modifying the software operation code to initiate an analysis interrupt may be awkward for an end user of the processor.